/*******************************************************************************
 *
 * Copyright (c) 2004-2008 by Vivante Corp.  All rights reserved.
 *
 * The material in this file is confidential and contains trade secrets of
 * Vivante Corporation.  This is proprietary information owned by Vivante
 * Corporation.  No part of this work may be disclosed, reproduced, copied,
 * transmitted, or used in any way for any purpose, without the express
 * written permission of Vivante Corporation.
 *
 ******************************************************************************/

/*******************************************************************************
 *
 * This file is automatically generated on Mon Apr 13 01:22:32 2009
 *
 * Any changes made to this file are lost at the next compile run!
 * So better make sure you update the source .r files instead!
 *
 ******************************************************************************/

////////////////////////////////////////////////////////////////////////////////
//                              ~~~~~~~~~~~~~~~~~                             //
//                              Module CommonUnit                             //
//                              ~~~~~~~~~~~~~~~~~                             //
////////////////////////////////////////////////////////////////////////////////

// Register AQPipeSelect.
// ~~~~~~~~~~~~~~~~~~~~~

// Select the current graphics pipe.

#define AQPipeSelectRegAddrs                                              0x0E00
#define AQ_PIPE_SELECT_Address                                           0x03800
#define AQ_PIPE_SELECT_MSB                                                    15
#define AQ_PIPE_SELECT_LSB                                                     0
#define AQ_PIPE_SELECT_Count                                                   1
#define AQ_PIPE_SELECT_FieldMask                                      0x00000001
#define AQ_PIPE_SELECT_ReadMask                                       0x00000001
#define AQ_PIPE_SELECT_WriteMask                                      0x00000001
#define AQ_PIPE_SELECT_ResetValue                                     0x00000000

// Selects the pipe to send states and data to.  Make 
// sure the PE is idle before you switch pipes.
#define AQ_PIPE_SELECT_PIPE                                                  0:0
#define AQ_PIPE_SELECT_PIPE_End                                                0
#define AQ_PIPE_SELECT_PIPE_Start                                              0
#define   AQ_PIPE_SELECT_PIPE_PIPE3D                                         0x0
#define   AQ_PIPE_SELECT_PIPE_PIPE2D                                         0x1

// Register AQEvent.
// ~~~~~~~~~~~~~~~~

// Send an event.

#define AQEventRegAddrs                                                   0x0E01
#define AQ_EVENT_Address                                                 0x03804
#define AQ_EVENT_MSB                                                          15
#define AQ_EVENT_LSB                                                           0
#define AQ_EVENT_Count                                                         1
#define AQ_EVENT_FieldMask                                            0x0000007F
#define AQ_EVENT_ReadMask                                             0x0000007F
#define AQ_EVENT_WriteMask                                            0x0000007F
#define AQ_EVENT_ResetValue                                           0x00000000

// 5-bit event ID to send.
#define AQ_EVENT_EVENT_ID                                                    4:0
#define AQ_EVENT_EVENT_ID_End                                                  4
#define AQ_EVENT_EVENT_ID_Start                                                0

// The event is sent by the FE.
#define AQ_EVENT_FE_SRC                                                      5:5
#define AQ_EVENT_FE_SRC_End                                                    5
#define AQ_EVENT_FE_SRC_Start                                                  5
#define   AQ_EVENT_FE_SRC_DISABLE                                            0x0
#define   AQ_EVENT_FE_SRC_ENABLE                                             0x1

// The event is sent by the PE.
#define AQ_EVENT_PE_SRC                                                      6:6
#define AQ_EVENT_PE_SRC_End                                                    6
#define AQ_EVENT_PE_SRC_Start                                                  6
#define   AQ_EVENT_PE_SRC_DISABLE                                            0x0
#define   AQ_EVENT_PE_SRC_ENABLE                                             0x1

// Register AQSemaphore.
// ~~~~~~~~~~~~~~~~~~~~

// A sempahore state arms the semaphore in the destination.

#define AQSemaphoreRegAddrs                                               0x0E02
#define AQ_SEMAPHORE_Address                                             0x03808
#define AQ_SEMAPHORE_MSB                                                      15
#define AQ_SEMAPHORE_LSB                                                       0
#define AQ_SEMAPHORE_Count                                                     1
#define AQ_SEMAPHORE_FieldMask                                        0x00001F1F
#define AQ_SEMAPHORE_ReadMask                                         0x00001F1F
#define AQ_SEMAPHORE_WriteMask                                        0x00001F1F
#define AQ_SEMAPHORE_ResetValue                                       0x00000000

#define AQ_SEMAPHORE_SOURCE                                                  4:0
#define AQ_SEMAPHORE_SOURCE_End                                                4
#define AQ_SEMAPHORE_SOURCE_Start                                              0
#define   AQ_SEMAPHORE_SOURCE_FRONT_END                                     0x01
#define   AQ_SEMAPHORE_SOURCE_VERTEX_SHADER                                 0x02
#define   AQ_SEMAPHORE_SOURCE_PRIMITIVE_ASSEMBLY                            0x03
#define   AQ_SEMAPHORE_SOURCE_SETUP                                         0x04
#define   AQ_SEMAPHORE_SOURCE_RASTERIZER                                    0x05
#define   AQ_SEMAPHORE_SOURCE_PIXEL_SHADER                                  0x06
#define   AQ_SEMAPHORE_SOURCE_PIXEL_ENGINE                                  0x07
#define   AQ_SEMAPHORE_SOURCE_MEMORY_CONTROLLER                             0x08
#define   AQ_SEMAPHORE_SOURCE_DISPLAY_CONTROLLER0                           0x09
#define   AQ_SEMAPHORE_SOURCE_DISPLAY_CONTROLLER1                           0x0A
#define   AQ_SEMAPHORE_SOURCE_DRAWING_ENGINE                                0x0B
#define   AQ_SEMAPHORE_SOURCE_EVENT                                         0x0C
#define   AQ_SEMAPHORE_SOURCE_RESOLVE                                       0x0D

#define AQ_SEMAPHORE_DESTINATION                                            12:8
#define AQ_SEMAPHORE_DESTINATION_End                                          12
#define AQ_SEMAPHORE_DESTINATION_Start                                         8
#define   AQ_SEMAPHORE_DESTINATION_FRONT_END                                0x01
#define   AQ_SEMAPHORE_DESTINATION_VERTEX_SHADER                            0x02
#define   AQ_SEMAPHORE_DESTINATION_PRIMITIVE_ASSEMBLY                       0x03
#define   AQ_SEMAPHORE_DESTINATION_SETUP                                    0x04
#define   AQ_SEMAPHORE_DESTINATION_RASTERIZER                               0x05
#define   AQ_SEMAPHORE_DESTINATION_PIXEL_SHADER                             0x06
#define   AQ_SEMAPHORE_DESTINATION_PIXEL_ENGINE                             0x07
#define   AQ_SEMAPHORE_DESTINATION_MEMORY_CONTROLLER                        0x08
#define   AQ_SEMAPHORE_DESTINATION_DISPLAY_CONTROLLER0                      0x09
#define   AQ_SEMAPHORE_DESTINATION_DISPLAY_CONTROLLER1                      0x0A
#define   AQ_SEMAPHORE_DESTINATION_DRAWING_ENGINE                           0x0B
#define   AQ_SEMAPHORE_DESTINATION_EVENT                                    0x0C
#define   AQ_SEMAPHORE_DESTINATION_RESOLVE                                  0x0D

// Register AQFlush.
// ~~~~~~~~~~~~~~~~

// Flush the current pipe.

#define AQFlushRegAddrs                                                   0x0E03
#define AQ_FLUSH_Address                                                 0x0380C
#define AQ_FLUSH_MSB                                                          15
#define AQ_FLUSH_LSB                                                           0
#define AQ_FLUSH_Count                                                         1
#define AQ_FLUSH_FieldMask                                            0x0000001F
#define AQ_FLUSH_ReadMask                                             0x0000001F
#define AQ_FLUSH_WriteMask                                            0x0000001F
#define AQ_FLUSH_ResetValue                                           0x00000000

// Flush the depth cache in the RA and PE.
#define AQ_FLUSH_ZCACHE                                                      0:0
#define AQ_FLUSH_ZCACHE_End                                                    0
#define AQ_FLUSH_ZCACHE_Start                                                  0
#define   AQ_FLUSH_ZCACHE_DISABLE                                            0x0
#define   AQ_FLUSH_ZCACHE_ENABLE                                             0x1

// Flush the render target cache in the PE.
#define AQ_FLUSH_CCACHE                                                      1:1
#define AQ_FLUSH_CCACHE_End                                                    1
#define AQ_FLUSH_CCACHE_Start                                                  1
#define   AQ_FLUSH_CCACHE_DISABLE                                            0x0
#define   AQ_FLUSH_CCACHE_ENABLE                                             0x1

// Flush the texture cache through the pixel shader (PS). It should only flush data related to pixel shader textures.  Can be used with the VSTCache bit.
#define AQ_FLUSH_TCACHE                                                      2:2
#define AQ_FLUSH_TCACHE_End                                                    2
#define AQ_FLUSH_TCACHE_Start                                                  2
#define   AQ_FLUSH_TCACHE_DISABLE                                            0x0
#define   AQ_FLUSH_TCACHE_ENABLE                                             0x1

// Flush the 2D pixel cache.
#define AQ_FLUSH_PE2D_CACHE                                                  3:3
#define AQ_FLUSH_PE2D_CACHE_End                                                3
#define AQ_FLUSH_PE2D_CACHE_Start                                              3
#define   AQ_FLUSH_PE2D_CACHE_DISABLE                                        0x0
#define   AQ_FLUSH_PE2D_CACHE_ENABLE                                         0x1

// Flush the texture cache through vertex shader (VS). It should only flush Cache lines related VS texture.  Can be used with the TCache bit.
#define AQ_FLUSH_VST_CACHE                                                   4:4
#define AQ_FLUSH_VST_CACHE_End                                                 4
#define AQ_FLUSH_VST_CACHE_Start                                               4
#define   AQ_FLUSH_VST_CACHE_DISABLE                                         0x0
#define   AQ_FLUSH_VST_CACHE_ENABLE                                          0x1

// Register AQMMUFlush.
// ~~~~~~~~~~~~~~~~~~~

// Flush the virtual addrses lookup cache inside the MC.

#define AQMMUFlushRegAddrs                                                0x0E04
#define AQMMU_FLUSH_Address                                              0x03810
#define AQMMU_FLUSH_MSB                                                       15
#define AQMMU_FLUSH_LSB                                                        0
#define AQMMU_FLUSH_Count                                                      1
#define AQMMU_FLUSH_FieldMask                                         0x0000001F
#define AQMMU_FLUSH_ReadMask                                          0x0000001F
#define AQMMU_FLUSH_WriteMask                                         0x0000001F
#define AQMMU_FLUSH_ResetValue                                        0x00000000

// Flush the FE address translation caches.
#define AQMMU_FLUSH_FEMMU                                                    0:0
#define AQMMU_FLUSH_FEMMU_End                                                  0
#define AQMMU_FLUSH_FEMMU_Start                                                0
#define   AQMMU_FLUSH_FEMMU_DISABLE                                          0x0
#define   AQMMU_FLUSH_FEMMU_ENABLE                                           0x1

// Flush the RA address translation caches.
#define AQMMU_FLUSH_RAMMU                                                    1:1
#define AQMMU_FLUSH_RAMMU_End                                                  1
#define AQMMU_FLUSH_RAMMU_Start                                                1
#define   AQMMU_FLUSH_RAMMU_DISABLE                                          0x0
#define   AQMMU_FLUSH_RAMMU_ENABLE                                           0x1

// Flush the TX address translation caches.
#define AQMMU_FLUSH_TXMMU                                                    2:2
#define AQMMU_FLUSH_TXMMU_End                                                  2
#define AQMMU_FLUSH_TXMMU_Start                                                2
#define   AQMMU_FLUSH_TXMMU_DISABLE                                          0x0
#define   AQMMU_FLUSH_TXMMU_ENABLE                                           0x1

// Flush the PE render target address translation caches.
#define AQMMU_FLUSH_PEMMU                                                    3:3
#define AQMMU_FLUSH_PEMMU_End                                                  3
#define AQMMU_FLUSH_PEMMU_Start                                                3
#define   AQMMU_FLUSH_PEMMU_DISABLE                                          0x0
#define   AQMMU_FLUSH_PEMMU_ENABLE                                           0x1

// Flush the PE depth address translation caches.
#define AQMMU_FLUSH_PEZMMU                                                   4:4
#define AQMMU_FLUSH_PEZMMU_End                                                 4
#define AQMMU_FLUSH_PEZMMU_Start                                               4
#define   AQMMU_FLUSH_PEZMMU_DISABLE                                         0x0
#define   AQMMU_FLUSH_PEZMMU_ENABLE                                          0x1

// Register AQVertexElementConfig.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

// For GC500 this always needs to be programmed to SIZE8.

#define AQVertexElementConfigRegAddrs                                     0x0E05
#define AQ_VERTEX_ELEMENT_CONFIG_Address                                 0x03814
#define AQ_VERTEX_ELEMENT_CONFIG_MSB                                          15
#define AQ_VERTEX_ELEMENT_CONFIG_LSB                                           0
#define AQ_VERTEX_ELEMENT_CONFIG_Count                                         1
#define AQ_VERTEX_ELEMENT_CONFIG_FieldMask                            0x00000001
#define AQ_VERTEX_ELEMENT_CONFIG_ReadMask                             0x00000001
#define AQ_VERTEX_ELEMENT_CONFIG_WriteMask                            0x00000001
#define AQ_VERTEX_ELEMENT_CONFIG_ResetValue                           0x00000000

// 0: VS output buffer can hold 4 vertices.
// 1: VS output buffer can hold 8 vertices.
#define AQ_VERTEX_ELEMENT_CONFIG_VS_OUTPUT_BUFFER                            0:0
#define AQ_VERTEX_ELEMENT_CONFIG_VS_OUTPUT_BUFFER_End                          0
#define AQ_VERTEX_ELEMENT_CONFIG_VS_OUTPUT_BUFFER_Start                        0
#define   AQ_VERTEX_ELEMENT_CONFIG_VS_OUTPUT_BUFFER_SIZE4                    0x0
#define   AQ_VERTEX_ELEMENT_CONFIG_VS_OUTPUT_BUFFER_SIZE8                    0x1

// Register gcregMultiSampleConfig.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

// Multi-Sample configuration register.

#define gcregMultiSampleConfigRegAddrs                                    0x0E06
#define GCREG_MULTI_SAMPLE_CONFIG_Address                                0x03818
#define GCREG_MULTI_SAMPLE_CONFIG_MSB                                         15
#define GCREG_MULTI_SAMPLE_CONFIG_LSB                                          0
#define GCREG_MULTI_SAMPLE_CONFIG_Count                                        1
#define GCREG_MULTI_SAMPLE_CONFIG_FieldMask                           0x000001FB
#define GCREG_MULTI_SAMPLE_CONFIG_ReadMask                            0x000001FB
#define GCREG_MULTI_SAMPLE_CONFIG_WriteMask                           0x000001FB
#define GCREG_MULTI_SAMPLE_CONFIG_ResetValue                          0x00000000

// Multi-Sample mode.
#define GCREG_MULTI_SAMPLE_CONFIG_MODE                                       1:0
#define GCREG_MULTI_SAMPLE_CONFIG_MODE_End                                     1
#define GCREG_MULTI_SAMPLE_CONFIG_MODE_Start                                   0
#define   GCREG_MULTI_SAMPLE_CONFIG_MODE_OFF                                 0x0
#define   GCREG_MULTI_SAMPLE_CONFIG_MODE_MSAA2                               0x1
#define   GCREG_MULTI_SAMPLE_CONFIG_MODE_MSAA4                               0x2

// Mask bits 1:0.
#define GCREG_MULTI_SAMPLE_CONFIG_MASK_MODE                                  3:3
#define GCREG_MULTI_SAMPLE_CONFIG_MASK_MODE_End                                3
#define GCREG_MULTI_SAMPLE_CONFIG_MASK_MODE_Start                              3
#define   GCREG_MULTI_SAMPLE_CONFIG_MASK_MODE_ENABLED                        0x0
#define   GCREG_MULTI_SAMPLE_CONFIG_MASK_MODE_MASKED                         0x1

// Multi-Sample enable bits.  If all bits are zero, then
// the attributes will be computed as if multi-sampling
// is disabled, but the resulting pixel will be replicated
// inside the render target and depth buffer.
#define GCREG_MULTI_SAMPLE_CONFIG_ENABLE                                     7:4
#define GCREG_MULTI_SAMPLE_CONFIG_ENABLE_End                                   7
#define GCREG_MULTI_SAMPLE_CONFIG_ENABLE_Start                                 4

// Mask bits 7:4.
#define GCREG_MULTI_SAMPLE_CONFIG_MASK_ENABLE                                8:8
#define GCREG_MULTI_SAMPLE_CONFIG_MASK_ENABLE_End                              8
#define GCREG_MULTI_SAMPLE_CONFIG_MASK_ENABLE_Start                            8
#define   GCREG_MULTI_SAMPLE_CONFIG_MASK_ENABLE_ENABLED                      0x0
#define   GCREG_MULTI_SAMPLE_CONFIG_MASK_ENABLE_MASKED                       0x1

